1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a vertical MOS transistor having a trench structure.
2. Description of the Related Art
There is a tendency that the chip size of a power supply IC represented by a voltage regulator and a voltage detector is reducing and output current of the voltage regulator is increasing. Among elements forming the power supply IC, a driver element for supplying current occupies a large part of the chip area, and thus, up to now, by adopting a MOS transistor having a trench structure, higher drive capability is sought through reduction in area and increase in effective channel width.
For example, Japanese Published Patent Applications 2003-101027 and H08-255901 present a conventional semiconductor device having a trench structure and a method of manufacturing the same.
A method of manufacturing a conventional vertical MOS transistor having a trench structure is described with reference to FIGS. 4A to 4H, which are schematic sectional views illustrating steps of the manufacturing method.
First, as illustrated in FIG. 4A, a first conductivity type well diffusion layer 23 (referred to as body) is formed in a region which includes a second conductivity type buried layer 22 and has a trench structure. A thermal oxide film 24 and a deposited oxide film 25 are stacked on the surface. A resist film 26 is used to pattern these oxide films to be used as a hard mask for trench etching. Then, as illustrated in FIG. 4B, after the resist film 26 is removed, etching is carried out using the hard mask formed by the stacked and patterned thermal oxide film 24 and deposited oxide film 25 to form a trench 27. Then, as illustrated in FIG. 4C, after the thermal oxide film 24 and the deposited oxide film 25 which are used as the hard mask are removed, a sacrificial oxide film 28 is formed by thermal oxidation for the purpose of improving the shape of the trench 27.
After that, as illustrated in FIG. 4D, the sacrificial oxide film 28 is removed, a gate insulating film 29 is formed by thermal oxidation, and further, a doped polycrystalline silicon film 30 doped with impurities is deposited. Then, as illustrated in FIG. 4E, by patterning using a resist film 32 and overetching the doped polycrystalline silicon film 30, a gate electrode 31 is obtained. Further, as illustrated in FIG. 4F, a resist film 33 is patterned and second conductivity type impurities are doped for the purpose of forming a source region, and then, as illustrated in FIG. 4G, a resist film 34 is newly patterned and first conductivity type impurities are doped for the purpose of forming a substrate potential region.
After that, as illustrated in FIG. 4H, a second conductivity type source heavily doped diffusion layer 35 and a first conductivity type substrate potential heavily doped diffusion layer 36 are formed by heat treatment. Then, after an interlayer insulating film 37 is deposited, a contact hole 38 for electrical connection of the gate electrode 31, the second conductivity type source heavily doped diffusion layer 35, and the first conductivity type substrate potential heavily doped diffusion layer 36 are formed. Then, plugs of tungsten or the like are embedded, and source substrate common potential wiring 40 and gate potential wiring 39 are formed.
In this way, an element structure of a vertical MOS transistor having a trench structure which vertically passes current and which includes the trench 27 formed in the first conductivity type well diffusion layer 23 is prepared.
However, in a vertical MOS transistor having a trench structure, when self-aligned silicidation is carried out for the purpose of reducing resistance of the contact for electrical connection of the gate electrode embedded in the trench, there is a problem that a silicide on the gate electrode embedded in the trench and a silicide on the substrate potential heavily doped diffusion layer and the source heavily doped diffusion layer adjacent to the trench are brought into electrical continuity. Accordingly, there is a problem that silicification on the gate electrode is difficult, and, when the width of the trench is reduced for the purpose of reducing the chip area, the resistance of the gate electrode increases.